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@BOOK{Ashenden2007,
  title = {{Digital Design An Embedded Systems Approach Using VHDL}},
  publisher = {Morgan Kaufmann},
  year = {2007},
  author = {Ashenden, Peter J}
}

@ARTICLE{Avissar2002,
  author = {Avissar, Oren and Barua, Rajeev and Stewart, Dave},
  title = {{An optimal memory allocation scheme for scratch-pad-based embedded
	systems}},
  journal = {ACM Trans. Embed. Comput. Syst.},
  year = {2002},
  volume = {1},
  pages = {6--26},
  number = {1},
  month = nov,
  address = {New York, NY, USA},
  doi = {10.1145/581888.581891},
  issn = {1539-9087},
  keywords = { allocation, embedded, heterogeneous, storage,Memory},
  publisher = {ACM},
  url = {http://doi.acm.org/10.1145/581888.581891}
}

@INPROCEEDINGS{Bak2009,
  author = {Bak, S and Betti, E and Pellizzoni, R and Caccamo, M and Sha, L},
  title = {{Real-time control of i/o cots peripherals for embedded systems}},
  booktitle = {Real-Time Systems Symposium, 2009, RTSS 2009. 30th IEEE},
  year = {2009},
  pages = {193--203},
  organization = {IEEE}
}

@ARTICLE{Bak2012,
  author = {Bak, Stanley and Yao, Gang and Pellizzoni, Rodolfo and Caccamo, Marco},
  title = {{Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems}},
  journal = {2012 IEEE International Conference on Embedded and Real-Time Computing
	Systems and Applications},
  year = {2012},
  pages = {300--309},
  month = aug,
  doi = {10.1109/RTCSA.2012.48},
  file = {:D$\backslash$:/Google Drive/Mendeley/2012/2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications/Bak et al/Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems - 2012.pdf:pdf},
  isbn = {978-1-4673-3017-6},
  publisher = {Ieee},
  url = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6300162}
}

@INPROCEEDINGS{Banakar2002a,
  author = {Banakar, Rajeshwari and Steinke, Stefan and Lee, BS Bo-Sik and Balakrishnan,
	M. and Marwedel, Peter},
  title = {{Scratchpad memory: design alternative for cache on-chip memory in
	embedded systems}},
  booktitle = {Proceedings of the \ldots},
  year = {2002},
  pages = {73},
  address = {New York, New York, USA},
  month = may,
  publisher = {ACM Press},
  annote = { From Duplicate 1 ( Scratchpad memory: design alternative for cache
	on-chip memory in embedded systems - Banakar, R; Steinke, S; Lee,
	BS )
	
	
	
	
	 },
  doi = {10.1145/774789.774805},
  file = {:D$\backslash$:/Google Drive/Mendeley/2002/Proceedings of the \ldots/Banakar et al/Scratchpad memory design alternative for cache on-chip memory in embedded systems - 2002.pdf:pdf},
  isbn = {1581135424},
  url = {http://dl.acm.org/citation.cfm?id=774805 http://dl.acm.org/citation.cfm?id=774789.774805}
}

@TECHREPORT{Bandyopadhyay2008,
  author = {Bandyopadhyay, S and Huining, F and Patel, H and Lee, E},
  title = {{A scratchpad memory allocation scheme for dataflow models}},
  institution = {Citeseer},
  year = {2008}
}

@ARTICLE{Beazley2001,
  author = {Beazley, D M and Ward, B D and Cooke, I R},
  title = {{The inside story on shared libraries and dynamic loading}},
  journal = {Computing in Science \& Engineering},
  year = {2001},
  volume = {3},
  pages = {90--97},
  number = {5},
  doi = {10.1109/5992.947112}
}

@INPROCEEDINGS{Chase1990,
  author = {Chase, D R and Wegman, M and Zadeck, F K},
  title = {{Analysis of pointers and structures}},
  booktitle = {ACM SIGPLAN Notices},
  year = {1990},
  volume = {25},
  number = {6},
  pages = {296--310},
  organization = {ACM}
}

@ARTICLE{Chu2001,
  author = {Chu, Y},
  title = {{Cache and branch prediction improvements for advanced computer architecture}},
  year = {2001},
  file = {:D$\backslash$:/Google Drive/Mendeley/2001/Unknown/Chu/Cache and branch prediction improvements for advanced computer architecture - 2001.pdf:pdf},
  url = {https://circle.ubc.ca/handle/2429/13689}
}

@INCOLLECTION{Deharbe2009,
  author = {D\'{e}harbe, David and Galv\~{a}o, Stephenson and Moreira, Anamaria},
  title = {{Formalizing FreeRTOS: First Steps}},
  booktitle = {Formal Methods Foundations and Applications},
  publisher = {Springer Verlag},
  year = {2009},
  editor = {Oliveira, Marcel Vin\'{\i}cius Medeiros and Woodcock, Jim},
  volume = {5902},
  series = {Lecture Notes in Computer Science},
  pages = {101--117},
  abstract = {This paper presents the current state of the formal development of
	FreeRTOS, a real-time operating system. The goal of this effort is
	to address a scientific challenge and is realized within the scope
	of the Grand Challenge on Verified Software. The development is realized
	with the B method. A model of the main functionalities of the FreeRTOS
	is now available and can be a starting point to establish an agreed
	formal specification of FreeRTOS that can be used by the research
	community.},
  doi = {10.1007/978-3-642-10452-7\_8},
  isbn = {9783642104510},
  url = {http://www.springerlink.com/content/4172354m1r33876p}
}

@INPROCEEDINGS{Deverge2007,
  author = {Deverge, J.-F. and Puaut, I},
  title = {{WCET-Directed Dynamic Scratchpad Memory Allocation of Data}},
  booktitle = {Real-Time Systems, 2007. ECRTS '07. 19th Euromicro Conference on},
  year = {2007},
  pages = {179--190},
  month = jul,
  abstract = {Many embedded systems feature processors coupled with a small and
	fast scratchpad memory. To the difference with caches, allocation
	of data to scratchpad memory must be handled by software. The major
	gain is to enhance the predictability of memory accesses latencies.
	A compile-time dynamic allocation approach enables eviction and placement
	of data to the scratchpad memory at runtime. Previous dynamic scratchpad
	memory allocation approaches aimed to reduce average-case program
	execution time or the energy consumption due to memory accesses.
	For real-time systems, worst-case execution time is the main metric
	to optimize. In this paper, we propose a WCET-directed algorithm
	to dynamically allocate static data and stack data of a program to
	scratchpad memory. The granularity of placement of memory transfers
	(e.g. on function, basic block boundaries) is discussed from the
	perspective of its computation complexity and the quality of allocation.},
  doi = {10.1109/ECRTS.2007.37},
  issn = {1068-3070},
  keywords = {WCET-directed dynamic scratchpad memory allocation}
}

@ARTICLE{KaivalyaM.Dixit1993,
  author = {Dixit, Kaivalya M.},
  title = {{Overview of the SPEC Benchmarks}},
  journal = {The Benchmark Handbook},
  year = {1993},
  pages = {489--521},
  chapter = {9},
  file = {:D$\backslash$:/Google Drive/Mendeley/1993/The Benchmark Handbook/Dixit/Overview of the SPEC Benchmarks - 1993.pdf:pdf},
  publisher = {Morgan Kaufmann Publishers}
}

@INPROCEEDINGS{Edwards2007,
  author = {Edwards, S A and Lee, E A},
  title = {{The case for the precision timed (PRET) machine}},
  booktitle = {Proceedings of the 44th annual Design Automation Conference},
  year = {2007},
  pages = {264--265},
  organization = {ACM}
}

@INPROCEEDINGS{Egger2006,
  author = {Egger, Bernhard and Lee, Jaejin and Shin, Heonshik},
  title = {{Scratchpad memory management for portable systems with a memory
	management unit}},
  booktitle = {Proceedings of the 6th ACM \& IEEE International conference on Embedded
	software},
  year = {2006},
  series = {EMSOFT '06},
  pages = {321--330},
  address = {New York, NY, USA},
  publisher = {ACM},
  doi = {10.1145/1176887.1176933},
  file = {:D$\backslash$:/Google Drive/Mendeley/2006/Proceedings of the 6th ACM \& IEEE International conference on Embedded software/Egger, Lee, Shin/Scratchpad memory management for portable systems with a memory management unit - 2006.pdf:pdf},
  isbn = {1-59593-542-8},
  keywords = {code placement,compilers,heterogeneous memory,paging,portable systems,postpass
	optimization,scratchpad,virtual memory},
  url = {http://doi.acm.org.proxy.lib.uwaterloo.ca/10.1145/1176887.1176933}
}

@INPROCEEDINGS{Francesco2004,
  author = {Francesco, Poletti and Marchal, Paul and Atienza, David and Benini,
	Luca and Catthoor, Francky and Mendias, Jose M},
  title = {{An integrated hardware/software approach for run-time scratchpad
	management}},
  booktitle = {Proceedings of the 41st annual Design Automation Conference},
  year = {2004},
  series = {DAC '04},
  pages = {238--243},
  address = {New York, NY, USA},
  publisher = {ACM},
  doi = {10.1145/996566.996634},
  file = {:D$\backslash$:/Google Drive/Mendeley/2004/Proceedings of the 41st annual Design Automation Conference/Francesco et al/An integrated hardwaresoftware approach for run-time scratchpad management - 2004.pdf:pdf},
  isbn = {1-58113-828-8},
  keywords = {AMBA AHB,DMA,dynamic allocation,scratchpad},
  url = {http://doi.acm.org/10.1145/996566.996634}
}

@MISC{Gaeke2002,
  author = {Gaeke, B R and Husbands, P and Li, X S and Oliker, L and Yelick,
	K A and Biswas, R},
  title = {{Memory-intensive benchmarks: IRAM vs. cache-based machines}},
  year = {2002},
  abstract = {The increasing gap between processor and memory performance has led
	to new architectural models for memory-intensive applications. In
	this paper, we use a set of memory-intensive benchmarks to evaluate
	a mixed logic and DRAM processor called VIRAM as a building block
	for scientific computing. For each benchmark, we explore the fundamental
	hardware requirements of the problem as well as alternative algorithms
	and data structures that can help expose fine-grained parallelism
	or simplify memory access patterns. Results indicate that VIRAM is
	significantly faster than conventional cache-based machines for problems
	that are truly limited by the memory system and that it has a significant
	power advantage across all the benchmarks},
  booktitle = {Proceedings 16th International Parallel and Distributed Processing
	Symposium},
  doi = {10.1109/IPDPS.2002.1015506},
  isbn = {0769515738},
  pages = {290--296},
  publisher = {IEEE Comput. Soc},
  url = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1015506}
}

@ARTICLE{Gough2004,
  author = {Gough, B and Stallman, R},
  title = {{An Introduction to GCC}},
  journal = {Network Theory, Ltd},
  year = {2004},
  publisher = {Citeseer}
}

@INPROCEEDINGS{Gustafsson2010,
  author = {Gustafsson, Jan and Betts, Adam and Ermedahl, Andreas and Lisper,
	Bj\"{o}rn},
  title = {{The \{M\{\"{a}\}lardalen\} \{WCET\} Benchmarks -- Past, Present
	and Future}},
  year = {2010},
  editor = {Lisper, Bj\"{o}rn},
  pages = {137--147},
  address = {Brussels, Belgium},
  month = jul,
  publisher = {OCG},
  keywords = {Benchmarks}
}

@BOOK{Hamplen2010,
  title = {{Rapid Prototyping Of Digital Systems}},
  publisher = {Springer},
  year = {2010},
  author = {Hamplen, J O and Hall, T S and Furman, M D}
}

@MISC{Hu2009,
  author = {Hu, Wei Hu Wei and Chen, Tianzhou Chen Tianzhou and Shi, Qingsong
	Shi Qingsong and Sha, Feng Sha Feng},
  title = {{Efficient utilization of scratch-pad memory for embedded systems}},
  year = {2009},
  abstract = {Hierarchy memory units are used in embedded systems for their different
	performance. The scratch-pad memory has been used to meet the real-time
	constraints in embedded systems. This paper presents an efficient
	compiler-assisted approach based on scratch-pad memory for heap and
	stack management of embedded systems. The stack and heap will be
	mapped to scratch-pad memory and some special code will be inserted
	into programs. Thus the heap and stack of the same program will be
	allocated to scratch-pad memory together. Results of the benchmarks
	show a 17\% reduction in runtime from our strategy vs. using the
	strategy that the heap and stack are allocated to off-chip memory.},
  booktitle = {2009 IEEE International Conference on Pervasive Computing and Communications},
  doi = {10.1109/PERCOM.2009.4912829},
  isbn = {9781424433049},
  keywords = {embedded system,optimization memory management,scratch pad memory},
  pages = {1--6}
}

@BOOK{DigitalICs_2002,
  title = {{Digital Integrated Circuits}},
  publisher = {Prentice-Hall},
  year = {2002},
  author = {{Jan M. Rabaey, Anantha Chandrakasan}, and Borivoje Nikolic}
}

@MISC{Kandemir2001,
  author = {Kandemir, M and Ramanujam, J and Irwin, M J and Vijaykrishnan, N
	and Kadayif, I and Parikh, A},
  title = {{Dynamic management of scratch-pad memory space}},
  year = {2001},
  abstract = {Optimizations aimed at improving the efficiency of on-chip memories
	are extremely important. We propose a compiler-controlled dynamic
	on-chip scratch-pad memory (SPM) management framework that uses both
	loop and data transformations. Experimental results obtained using
	a generic cost model indicate significant reductions in data transfer
	activity between SPM and off-chip memory.},
  booktitle = {Proceedings of the 38th Design Automation Conference IEEE Cat No01CH37232},
  doi = {10.1109/DAC.2001.156226},
  isbn = {1581132972},
  issn = {0738100X},
  number = {i},
  pages = {690--695},
  publisher = {Acm},
  url = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=935595},
  volume = {3}
}

@ARTICLE{Lee2007,
  author = {Lee, EA},
  title = {{Computing foundations and practice for cyber-physical systems: A
	preliminary report}},
  journal = {University of California, Berkeley, Tech. Rep. UCB/ \ldots},
  year = {2007},
  file = {:D$\backslash$:/Google Drive/Mendeley/2007/University of California, Berkeley, Tech. Rep. UCB \ldots/Lee/Computing foundations and practice for cyber-physical systems A preliminary report - 2007.pdf:pdf},
  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-72.pdf}
}

@INPROCEEDINGS{Lee2006,
  author = {Lee, J and Park, J and Hong, S},
  title = {{Memory Footprint Reduction with Quasi-Static Shared Libraries in
	MMU-less Embedded Systems}},
  booktitle = {Real-Time and Embedded Technology and Applications Symposium, 2006.
	Proceedings of the 12th IEEE},
  year = {2006},
  pages = {24--36},
  organization = {IEEE}
}

@INPROCEEDINGS{Lewandowski2007,
  author = {Lewandowski, M and Stanovich, M J and Baker, T P and Gopalan, K and
	Wang, A I},
  title = {{Modeling device driver effects in real-time schedulability analysis:
	Study of a network driver}},
  booktitle = {Real Time and Embedded Technology and Applications Symposium, 2007.
	RTAS'07. 13th IEEE},
  year = {2007},
  pages = {57--68},
  organization = {IEEE}
}

@INPROCEEDINGS{Lickly2008,
  author = {Lickly, Ben and Liu, Isaac and Kim, Sungjun and Patel, Hiren D and
	Edwards, Stephen A and Lee, Edward A},
  title = {{Predictable programming on a precision timed architecture}},
  booktitle = {Proceedings of the 2008 international conference on Compilers, architectures
	and synthesis for embedded systems},
  year = {2008},
  series = {CASES '08},
  pages = {137--146},
  address = {New York, NY, USA},
  publisher = {ACM},
  annote = {This work requires a significant changes in the hardware architecture.
	it has awheel to access memory. each thread from the 6 thread has
	a fixed time to access memory. PRET},
  doi = {10.1145/1450095.1450117},
  file = {:C$\backslash$:/Documents and Settings/saud/Local Settings/Application Data/Mendeley Ltd./Mendeley Desktop/Downloaded/Lickly et al. - 2008 - Predictable programming on a precision timed architecture.pdf:pdf},
  isbn = {978-1-60558-469-0},
  keywords = {memory hierarchy,pipeline,timing predictability},
  url = {http://doi.acm.org.proxy.lib.uwaterloo.ca/10.1145/1450095.1450117}
}

@BOOK{Marwedel2010,
  title = {{Embedded system design: Embedded systems foundations of cyber-physical
	systems}},
  year = {2010},
  author = {Marwedel, P},
  file = {:D$\backslash$:/Google Drive/Mendeley/2010/Unknown/Marwedel/Embedded system design Embedded systems foundations of cyber-physical systems - 2010.pdf:pdf},
  url = {http://books.google.ca/books?hl=en\&lr=\&id=EXboa4sXlRsC\&oi=fnd\&pg=PR5\&dq=modern+embedded+system\&ots=LEka1cvslc\&sig=Mc\_gb2GVZWw5hSkldMhEqfilmck}
}

@ARTICLE{McIlroy2008,
  author = {McIlroy, Ross and Dickman, Peter and Sventek, Joe},
  title = {{Efficient dynamic heap allocation of scratch-pad memory}},
  journal = {Proceedings of the 7th international symposium on Memory management
	ISMM 08},
  year = {2008},
  pages = {31},
  abstract = {An increasing number of processor architectures support scratch-pad
	memory - software managed on-chip memory. Scratch-pad memory provides
	low latency data storage, like on-chip caches, but under explicit
	software control. The simple design and predictable nature of scratchpad
	memories has seen them incorporated into a number of embedded and
	real-time system processors. They are also employed by multi-core
	architectures to isolate processor core local data and act as low
	latency inter-core shared memory. Managing scratch-pad memory by
	hand is time consuming, error prone and potentially wasteful; tools
	that automatically manage this memory are essential for its use by
	general purpose software. While there has been promising work in
	compile time allocation of scratch-pad memory, there will always
	be applications which require run-time allocation. Modern dynamic
	memory management techniques are too heavy-weight for scratch-pad
	management. This paper presents the Scratch-Pad Memory Allocator,
	a light-weight memory management algorithm, specifically designed
	to manage small on-chip memories. This algorithm uses a variety of
	techniques to reduce its memory footprint while still remaining effective,
	including: representing memory both as fixed-sized blocks and variable-sized
	regions within these blocks; coding of memory state in bitmap structures;
	and exploiting the layout of adjacent regions to dispense with boundary
	tags for split and coalesce operations. We compare the performance
	of this allocator against Doug Lea's malloc implementation for the
	management of core-local and inter-core shared scratchpad memories
	under real world memory traces. This algorithm manages small memories
	efficiently and scales well under load when multiple competing cores
	access shared memory.},
  doi = {10.1145/1375634.1375640},
  isbn = {9781605581347},
  publisher = {ACM Press},
  url = {http://portal.acm.org/citation.cfm?doid=1375634.1375640}
}

@ARTICLE{Moura2008,
  author = {Moura, L De and Bj\o rner, N},
  title = {{Z3: An efficient SMT solver}},
  journal = {Tools and Algorithms for the Construction and Analysis of Systems},
  year = {2008},
  file = {:D$\backslash$:/Google Drive/Mendeley/2008/Tools and Algorithms for the Construction and Analysis of Systems/Moura, Bj\o rner/Z3 An efficient SMT solver - 2008.pdf:pdf},
  url = {http://www.springerlink.com.proxy.lib.uwaterloo.ca/index/60HX121083823548.pdf}
}

@INPROCEEDINGS{Muck2011,
  author = {Muck, Tiago Rogerio and Frohlich, Antonio Augusto},
  title = {{Run-time scratch-pad memory management for embedded systems}},
  booktitle = {IECON 2011 - 37th Annual Conference on IEEE Industrial Electronics
	Society},
  year = {2011},
  pages = {2833--2838},
  organization = {Software/Hardware Integration Lab, Federal University of Santa Catarina,
	Florian\&\#x00F3;polis, Brazil},
  publisher = {IEEE},
  abstract = {Scratch-pad memories (SPM) are being increasingly used in embedded
	systems due to their higher energy and silicon area efficiency in
	comparison to ordinary caches. However, in order to exploit all of
	its advantages, efficient memory allocation mechanisms must be provided.
	In this work we propose a run-time memory management approach for
	SPMs at OS-level that can be combined with other compile-time approaches.
	The operating system memory manager takes annotations inserted into
	the code by the programmer as hints to choose the most appropriate
	memory (i.e. main memory or SPM) for each allocation. Experimental
	results confirm the approach's efficiency when compared to a similar
	compile-time technique.},
  doi = {10.1109/IECON.2011.6119761},
  file = {:D$\backslash$:/Google Drive/Mendeley/2011/IECON 2011 - 37th Annual Conference on IEEE Industrial Electronics Society/Muck, Frohlich/Run-time scratch-pad memory management for embedded systems - 2011.pdf:pdf},
  isbn = {9781612849713},
  issn = {1553-572X},
  keywords = {SPM,compile-time approach,embedded systems,main me}
}

@ARTICLE{Musmanno2003,
  author = {Musmanno, J},
  title = {{Data Intensive Systems (DIS) Benchmark Performance Summary}},
  year = {2003},
  file = {:D$\backslash$:/Google Drive/Mendeley/2003/Unknown/Musmanno/Data Intensive Systems (DIS) Benchmark Performance Summary - 2003.pdf:pdf},
  url = {http://oai.dtic.mil/oai/oai?verb=getRecord\&metadataPrefix=html\&identifier=ADA418752}
}

@MISC{Ozturk2006,
  author = {Ozturk, O and Kandemir, M and Kolcu, I},
  title = {{Shared scratch-pad memory space management}},
  year = {2006},
  abstract = {Scratch-pad memories (SPMs) are important storage components in many
	embedded applications and used as an alternative or a complimentary
	storage to on-chip cache memories. One of the most critical issues
	in the context of SPMs is to select the data elements to place in
	them since the gap between SPM access latencies and off-chip memory
	access latencies keep increasing dramatically. Previous research
	considered this problem and attacked it using both static and dynamic
	schemes. Most of the prior efforts on data SPMs have mainly focused
	on single application scenarios, i.e., the SPM space available is
	assumed to be managed by a single application at any given time.
	While this assumption makes sense in certain domains, there also
	exist many cases where multiple applications need to share the same
	SPM space. This paper focuses on such a multi-application scenario
	and proposes a nonuniform SPM space partitioning and management across
	concurrently-executing applications. In our approach, the amount
	of data to be allocated to each application is decided based on the
	data reuse each application exhibits},
  booktitle = {7th International Symposium on Quality Electronic Design ISQED06},
  doi = {10.1109/ISQED.2006.115},
  isbn = {0769525237},
  pages = {6 pp.--584},
  publisher = {IEEE Computer Society},
  url = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1613200}
}

@ARTICLE{Panda1997,
  author = {Panda, PR and Dutt, ND and Nicolau, A},
  title = {{Efficient utilization of scratch-pad memory in embedded processor
	applications}},
  journal = {\ldots of the 1997 European conference on \ldots},
  year = {1997},
  file = {:D$\backslash$:/Google Drive/Mendeley/1997/\ldots of the 1997 European conference on \ldots/Panda, Dutt, Nicolau/Efficient utilization of scratch-pad memory in embedded processor applications - 1997.pdf:pdf},
  url = {http://dl.acm.org/citation.cfm?id=787762}
}

@INPROCEEDINGS{Park2007,
  author = {Park, Soyoung and Park, Hae-woo and Ha, Soonhoi},
  title = {{A Novel Technique to Use Scratch-pad Memory for Stack Management}},
  booktitle = {Design, Automation Test in Europe Conference Exhibition, 2007. DATE
	'07},
  year = {2007},
  pages = {1--6},
  month = apr,
  abstract = {Extensive work has been done for optimal management of scratch-pad
	memory (SPM) all assuming that the SPM is assigned a fixed address
	space. The main target objects to be placed on the SPM have been
	code and global memory since their sizes and locations are not changed
	dynamically. We propose a novel idea of dynamic address mapping of
	SPM with the assistance of memory management unit (MMU). It allows
	us to use SPM for stack management without architecture modification
	and complier assistance. The proposed technique is orthogonal to
	the previous works so can be used at the same time. Experiments results
	show that the proposed technique results in average performance improvement
	of 13\% and energy savings of 12\% observed compared to using only
	external DRAM. And it also gives noticeable speed up and energy saving
	against a typical cache solution for stack data},
  doi = {10.1109/DATE.2007.364509},
  file = {:D$\backslash$:/Google Drive/Mendeley/2007/Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07/Park, Park, Ha/A Novel Technique to Use Scratch-pad Memory for Stack Management - 2007.pdf:pdf},
  keywords = {SPM,architecture modification,cache solution,compl}
}

@INPROCEEDINGS{Pellizzoni2011,
  author = {Pellizzoni, R and Betti, E and Bak, S and Yao, G and Criswell, J
	and Caccamo, M and Kegley, R},
  title = {{A Predictable Execution Model for COTS-based Embedded Systems}},
  booktitle = {2011 17th IEEE Real-Time and Embedded Technology and Applications
	Symposium},
  year = {2011},
  pages = {269--279},
  organization = {IEEE},
  file = {:C$\backslash$:/Documents and Settings/saud/Local Settings/Application Data/Mendeley Ltd./Mendeley Desktop/Downloaded/Pellizzoni et al. - 2011 - A Predictable Execution Model for COTS-based Embedded Systems.pdf:pdf}
}

@BOOK{PhillipA.Laplante2004,
  title = {{Real-Time Systems Design and Analysis}},
  publisher = {IEEE Press \& Wiley-Interscience},
  year = {2004},
  author = {{Phillip A. Laplante}},
  edition = {Third Edit}
}

@INPROCEEDINGS{Prakash2012,
  author = {Prakash, Aayush and Patel, HD},
  title = {{An instruction scratchpad memory allocation for the precision timed
	architecture}},
  booktitle = {Design, Automation \& Test in Europe \ldots},
  year = {2012},
  file = {:D$\backslash$:/Google Drive/Mendeley/2012/Design, Automation \& Test in Europe \ldots/Prakash, Patel/An instruction scratchpad memory allocation for the precision timed architecture - 2012.pdf:pdf},
  isbn = {9783981080186},
  url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=6176553}
}

@INPROCEEDINGS{Puaut2007,
  author = {Puaut, I and Pais, C},
  title = {{Scratchpad memories vs locked caches in hard real-time systems:
	a quantitative comparison}},
  booktitle = {Design, Automation Test in Europe Conference Exhibition, 2007. DATE
	'07},
  year = {2007},
  pages = {1--6},
  month = apr,
  abstract = {We propose in this paper an algorithm for off-line selection of the
	contents of on-chip memories. The algorithm supports two types of
	on-chip memories, namely locked caches and scratchpad memories. The
	contents of on-chip memory, although selected off-line, is changed
	at run-time, for the sake of scalability with respect to task size.
	Experimental results show that the algorithm yields to good ratios
	of on-chip memory accesses on the worst-case execution path, with
	a tolerable reload overhead, for both types of on-chip memories.
	Furthermore, we highlight the circumstances under which one type
	of on-chip memory is more appropriate than the other depending of
	architectural parameters (cache block size) and application characteristics
	(basic block size)},
  doi = {10.1109/DATE.2007.364510},
  file = {:D$\backslash$:/Google Drive/Mendeley/2007/Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07/Puaut, Pais/Scratchpad memories vs locked caches in hard real-time systems a quantitative comparison - 2007.pdf:pdf},
  keywords = {hard real-time systems,locked caches,off line sele}
}

@ARTICLE{Sha2004,
  author = {Sha, L},
  title = {{Real-time virtual machines for avionics software porting and development}},
  journal = {Real-Time and Embedded Computing Systems and Applications},
  year = {2004},
  url = {http://www.springerlink.com/index/x33dt8890lwagqdu.pdf}
}

@INPROCEEDINGS{Suhendra2008,
  author = {Suhendra, V and Mitra, T},
  title = {{Exploring locking \& partitioning for predictable shared caches
	on multi-cores}},
  booktitle = {Proceedings of the 45th annual Design Automation Conference},
  year = {2008},
  pages = {300--303},
  organization = {ACM},
  file = {:D$\backslash$:/Google Drive/Mendeley/2008/Proceedings of the 45th annual Design Automation Conference/Suhendra, Mitra/Exploring locking \& partitioning for predictable shared caches on multi-cores - 2008.pdf:pdf}
}

@INPROCEEDINGS{Takase2010,
  author = {Takase, H and Tomiyama, H and Takada, H},
  title = {{Partitioning and allocation of scratch-pad memory for priority-based
	preemptive multi-task systems}},
  booktitle = {Design, Automation Test in Europe Conference Exhibition (DATE), 2010},
  year = {2010},
  pages = {1124--1129},
  month = mar,
  abstract = {Scratch-pad memory has been employed as a partial or entire replacement
	for cache memory due to its better energy efficiency. In this paper,
	we propose scratch-pad memory management techniques for priority-based
	preemptive multi-task systems. Our techniques are applicable to a
	real-time environment. The three methods which we propose, i.e.,
	spatial, temporal, and hybrid methods, bring about effective usage
	of the scratch-pad memory space, and achieve energy reduction in
	the instruction memory subsystems. We formulate each method as an
	integer programming problem that simultaneously determines (1) partitioning
	of scratch-pad memory space for the tasks, and (2) allocation of
	program code to scratch-pad memory space for each task. It is remarkable
	that periods and priorities of tasks are considered in the formulas.
	Additionally, we implement an RTOS-hardware cooperative support mechanism
	for a runtime code allocation to the scratch-pad memory space. We
	have made the experiments with the fully functional real-time operating
	system. The experimental results with four task sets have demonstrated
	the effectiveness of our techniques. Up to 73\% energy reduction
	compared to a standard method was achieved.},
  issn = {1530-1591},
  keywords = {RTOS-hardware cooperative support mechanism;cache }
}

@MISC{Takase2010a,
  author = {Takase, Hideki Takase Hideki and Tomiyama, H and Takada, H},
  title = {{Partitioning and allocation of scratch-pad memory for priority-based
	preemptive multi-task systems}},
  year = {2010},
  abstract = {This paper proposes three approaches for allocation of scratch-pad
	memory in non-preemptive fixed-priority multi-task systems. These
	approaches can reduce energy consumption of instruction memory. Each
	approach is formulated as an integer programming problem which simultaneously
	determines (1) partitioning of scratch-pad memory spaces for the
	tasks, and (2) allocation of functions to the scratch-pad memory
	space for each task. The experimental results show the effectiveness
	of the proposed approaches.},
  booktitle = {Design Automation amp Test in Europe Conference amp Exhibition DATE
	2010},
  doi = {10.1109/VDAT.2009.5158097},
  isbn = {9781424427819},
  issn = {15301591},
  pages = {1124--1129},
  url = {http://joi.jlc.jst.go.jp/JST.JSTAGE/ipsjtsldm/2.180?from=CrossRef},
  volume = {2}
}

@INPROCEEDINGS{Udayakumaran2003,
  author = {Udayakumaran, Sumesh and Barua, Rajeev},
  title = {{Compiler-decided dynamic memory allocation for scratch-pad based
	embedded systems}},
  booktitle = {Proceedings of the 2003 international conference on Compilers, architecture
	and synthesis for embedded systems},
  year = {2003},
  series = {CASES '03},
  pages = {276--286},
  address = {New York, NY, USA},
  publisher = {ACM},
  doi = {10.1145/951710.951747},
  isbn = {1-58113-676-5},
  keywords = { embedded systems, memory allocation, scratch-pad,compiler},
  url = {http://doi.acm.org/10.1145/951710.951747}
}

@INPROCEEDINGS{Wehmeyer2004,
  author = {Wehmeyer, L and Marwedel, P},
  title = {{Influence of onchip scratchpad memories on wcet prediction}},
  year = {2004},
  url = {https://www.irisa.fr/manifestations/2004/wcet2004/Papers/Wehmeyer.pdf}
}

@INPROCEEDINGS{Whitham2009,
  author = {Whitham, J and Audsley, N},
  title = {{Implementing time-predictable load and store operations}},
  booktitle = {Proc. EMSOFT},
  year = {2009},
  pages = {265--274},
  file = {:D$\backslash$:/Google Drive/Mendeley/2009/Proc. EMSOFT/Whitham, Audsley/Implementing time-predictable load and store operations - 2009.pdf:pdf}
}

@INPROCEEDINGS{Whitham2012,
  author = {Whitham, Jack and Audsley, Neil C.},
  title = {{Explicit Reservation of Local Memory in a Predictable, Preemptive
	Multitasking Real-Time System}},
  booktitle = {2012 IEEE 18th Real Time and Embedded Technology and Applications
	Symposium},
  year = {2012},
  pages = {3--12},
  month = apr,
  publisher = {IEEE},
  abstract = {This paper proposes Carousel, a mechanism to manage local memory space,
	i.e. cache or scratch pad memory (SPM), such that inter-task interference
	is completely eliminated. The cost of saving and restoring the local
	memory state across context switches is explicitly handled by the
	preempting task, rather than being imposed implicitly on preempted
	tasks. Unlike earlier attempts to eliminate inter-task interference,
	Carousel allows each task to use as much local memory space as it
	requires, permitting the approach to scale to large numbers of tasks.
	Carousel is experimentally evaluated using a simulator. We demonstrate
	that preemption has no effect on task execution times, and that the
	Carousel technique compares well to the conventional approach to
	handling interference, where worst-case interference costs are simply
	added to the worst-case execution times (WCETs) of lower-priority
	tasks.},
  annote = {1. special OS that support carousel functionaility 2. based on simulation
	2. using DMA how ever their mechanisim forces the CPU to wait until
	the transfer is finished. 3. their OS has to be in seperate SPM as
	if it is in the carousel it can be pushed out to the main memory
	(cannot easily be stored in Carousel because it must remain in local
	RAM at all times.). 4. The transilation unit is block-based. for
	many small blocks the fmax is compromised. for large blocks the translation
	is fast but the space utilization can be reduced. 5. using carousel
	, it becomes imposible to overlap the CPU with DMA, as Carousel shifts
	the reserving local RAM for taskti onto task $\tau$i itself. 6. Optimum
	local on-chip RAM utilization, in a great cost of loading and unloading
	time. },
  doi = {10.1109/RTAS.2012.19},
  file = {:D$\backslash$:/Google Drive/Mendeley/2012/2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium/Whitham, Audsley/Explicit Reservation of Local Memory in a Predictable, Preemptive Multitasking Real-Time System - 2012.pdf:pdf},
  isbn = {978-1-4673-0883-0},
  url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=6200073}
}

@ARTICLE{WhithamN2012,
  author = {Whitham, J and Davis, RI and Audsley, N and Altmeyer, S and Maiza,
	C},
  title = {{Investigation of Scratchpad Memory for Preemptive Multitasking}},
  journal = {jwhitham.org},
  file = {:D$\backslash$:/Google Drive/Mendeley/Unknown/jwhitham.org/Whitham et al/Investigation of Scratchpad Memory for Preemptive Multitasking - Unknown.pdf:pdf},
  url = {http://www.jwhitham.org/pubs/rtss12.pdf}
}

@MISC{de2-70,
  title = {{DE2-70} Development and Education Board},
  howpublished = {http://www.altera.com/education/univ /materials/boards/de2-70/unv-de2-70-board.html},
  url = {http://www.altera.com/education/univ/materials/boards/de2-70/unv-de2-70-board.html}
}

@MISC{ECE3055_cache,
  title = {{Cache Architecture, ECE 3055: Computer Architecture and Operating
	Systems}},
  howpublished = {http://users.ece.gatech.edu/~dblough/3055/},
  url = {http://users.ece.gatech.edu/~dblough/3055/},
  urldate = {10/11/2012}
}

@MISC{Modelsim_altera,
  title = {{ModelSim for Altera's devices}},
  howpublished = {http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html},
  url = {http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html}
}

@MISC{niosii_II,
  title = {{NiosII Embedded Processor}},
  howpublished = {http://www.altera.com/devices/processor/nios2/ni2-index.html},
  url = {http://www.altera.com/devices/processor/nios2/ni2-index.html}
}

@MISC{qsys_,
  title = {{Qsys : Altera System Integration Tool}},
  howpublished = {http://www.altera.com/products/software /quartus-ii/subscription-edition/qsys/qts-qsys.html},
  url = {http://www.altera.com/products/software/quartus-ii/subscription-edition/qsys/qts-qsys.html}
}

@MISC{quartus_,
  title = {{Quartus-II design software}},
  howpublished = {http://www.altera.com/products/software/quartus-ii/subscription-edition/design-entry-synthesis/qts-des-ent-syn.html},
  url = {http://www.altera.com/products/software/quartus-ii/subscription-edition/design-entry-synthesis/qts-des-ent-syn.html}
}

@MISC{spec_BM,
  title = {{SPEC Benchmarks}},
  howpublished = {http://www.spec.org/benchmarks.html},
  url = {http://www.spec.org/benchmarks.html}
}

@MISC{SPM_WIKI2012,
  title = {{Scratchpad memory}},
  howpublished = {http://en.wikipedia.org/wiki/Scratchpad\_memory},
  url = {http://en.wikipedia.org/wiki/Scratchpad\_memory},
  urldate = {18/11/2012}
}

